During the past years, the evolution of processors for computing devices such as computers, mobile phones, game consoles, personal digital assistants, etc., was driven by the concept of increasing the clock frequency and complexity of the chip, resulting then in an improved performance, i.e., solving computational jobs faster and in some cases more efficiently.
Recently, another concept for achieving the increase in the speed and efficiency of the processors is emerging. This new concept relies on the idea of using parallel computing to increase the system throughput without increasing the clock frequency. The idea of parallel computing is to split a problem that has to be solved, into several smaller independent problems, if possible. This split of the larger problem into smaller problems allows a system to use more than a processor and to compute simultaneously the smaller problems, in parallel, on the plural processors. According to this approach, it is possible to solve the large problem faster. Possible advantages of using multi-core architectures are flexibility and scalability.
However, by using plural processors in a single device may require higher energy consumption, as N processors are likely to use more energy than a single processor. Thus, the power consumption management of the plural processors has to be considered. The power consumption management needs also to address those situations in which some of the processors are used while the remaining processors are idle. This matter becomes more critical for mobile devices that have as the only source of energy a battery, i.e., a limited energy supply.
One way to consider the power consumption management is to reduce or temporarily turn off the voltage supply to the idle processors. However, reducing the voltage supply for an entire chip might not be possible due to performance constraints (wake-up times, etc.). Also, this technique has to consider which and how many processors to turn off and for how long, which is not an obvious task because the number of processors needed to perform a specific task depends on the specific task. For example, components of an application specific integrated circuit (ASIC) or a microprocessor have different requirements on voltage supply due to different critical paths. A critical path may be the largest amount of logic depth between two registers, where the logic depth may translate into a delay which is dependent on the supply voltage. Therefore, running some components on a lower voltage can save energy.
Furthermore, using multiple clock frequencies in a synchronous design can lead to a twofold energy saving in a multiple voltage supply environment, because decreasing the clock frequency in a complementary metal-oxide-semiconductor (CMOS) circuit makes it possible to reduce its supply voltage. Therefore, one possibility for reducing the energy consumption in a parallel computing system is scheduling techniques that provide a distribution of the computing job over the entire set of processor cores.
However, when dividing a computational job among a number of parallel computation units, instead of using a single computational unit at a higher clock frequency, N parallel units may be used at a reduced clock frequency. It is assumed that by using the N parallel units enables a clock frequency reduction by a factor N. In practice, due to overhead, it is found that the actual clock frequency reduction is less than N.
By only considering the linear relation between the dynamic power consumption and clock frequency and also considering that the parallel computation units consume more chip-area, it follows that the parallel implementation is less energy efficient than a single computation unit. However, to determine whether energy benefits exist for the parallel computation, the power consumed by the parallel computation units, due to the lower clock frequency, when using less pipeline registers and/or low-leakage transistors and/or lower supply voltage should be evaluated. Taking these factors into account, it may be shown that a parallel processor implementation can save energy compared to a single processor.
However, scheduling the processor resources in a parallel computing environment is complex because of the plurality of the existing resources, the different needs of each computing job, etc. In other words, because there are a very large number of possible combinations of the number of resources to be used and the number of the computing jobs to be performed, finding the appropriate scheduling of the resources is not a simple matter of trying a reduced number of possibilities. This challenge of finding the correct number of resources to be used for a specific computing job is problematic for the existing systems, which also makes the power consumption reduction difficult.
Accordingly, it would be desirable to provide devices, systems and methods that avoid the afore-described problems and drawbacks.